In recent years, attention has been paid to a wafer level chip size packaging technique in which wirings, protective films, and terminals are formed in a state of a wafer, and then the wafer is cut into individual pieces with a dicing machine or the like to form a package. In the wafer level chip size package, the size of the chip obtained by finally cutting the wafer becomes the size of the package, so that it is possible to reduce the size and weight of the chip.
For example, Patent Document 1 discloses a technique in which a plurality of electronic devices are provided on a substrate wafer, a cover wafer including a plurality of conductive paths extending therethrough is provided, and a plurality of conductive paths are aligned with a plurality of electronic devices of the substrate wafer, thereby aligning and bonding the cover wafer and the substrate wafer.
Patent Document 1: Japanese Patent No. 2,820,609